Conference Guide

The Lifecycle of an Instruction Set
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0:04Tom Forsyth: Welcome to the talk
0:04Tom Forsyth: Welcome to the talk
0:04Tom Forsyth: Welcome to the talk
0:34TF: The Lifecycle of an Instruction Set
0:34TF: The Lifecycle of an Instruction Set
0:34TF: The Lifecycle of an Instruction Set
1:41TF: Caveats1
1:41TF: Caveats1
1:41TF: Caveats1
2:32TF: Levels of hardware
2:32TF: Levels of hardware
2:32TF: Levels of hardware
5:28TF: Innovation in ISA (instruction set architecture)
5:28TF: Innovation in ISA (instruction set architecture)
5:28TF: Innovation in ISA (instruction set architecture)
7:17TF: Innovation becomes legacy!
7:17TF: Innovation becomes legacy!
7:17TF: Innovation becomes legacy!
8:54TF: Pixomatic (~2004)
8:54TF: Pixomatic (~2004)
8:54TF: Pixomatic (~2004)
9:55TF: SMCA (~2005)
9:55TF: SMCA (~2005)
9:55TF: SMCA (~2005)
11:42TF: SMCA New Instructions
11:42TF: SMCA New Instructions
11:42TF: SMCA New Instructions
12:51TF: How to develop an ISA
12:51TF: How to develop an ISA
12:51TF: How to develop an ISA
14:31TF: SMCA core choice
14:31TF: SMCA core choice
14:31TF: SMCA core choice
16:24TF: P54C pairing and "free" memory
16:24TF: P54C pairing and "free" memory
16:24TF: P54C pairing and "free" memory
17:46TF: P54C details shaped the ISA
17:46TF: P54C details shaped the ISA
17:46TF: P54C details shaped the ISA
18:45TF: SMCA to Larrabee
18:45TF: SMCA to Larrabee
18:45TF: SMCA to Larrabee
20:19TF: Larrabee features: Predication masks
20:19TF: Larrabee features: Predication masks
20:19TF: Larrabee features: Predication masks
22:53TF: Larrabee features: Register lane swizzles
22:53TF: Larrabee features: Register lane swizzles
22:53TF: Larrabee features: Register lane swizzles
24:39TF: Larrabee features: Memory swizzles
24:39TF: Larrabee features: Memory swizzles
24:39TF: Larrabee features: Memory swizzles
26:07TF: Larrabee features: Floating-point-Multiply-Add combos
26:07TF: Larrabee features: Floating-point-Multiply-Add combos
26:07TF: Larrabee features: Floating-point-Multiply-Add combos
26:10TF: Larrabee features: madd233
26:10TF: Larrabee features: madd233
26:10TF: Larrabee features: madd233
27:19TF: Larrabee features: Floating-point fixup
27:19TF: Larrabee features: Floating-point fixup
27:19TF: Larrabee features: Floating-point fixup
30:35TF: Larrabee features: Ternlogop
30:35TF: Larrabee features: Ternlogop
30:35TF: Larrabee features: Ternlogop
33:12TF: Larrabee 1 - Knights Ferry
33:12TF: Larrabee 1 - Knights Ferry
33:12TF: Larrabee 1 - Knights Ferry
35:15TF: Larrabee 2 - Knights Corner
35:15TF: Larrabee 2 - Knights Corner
35:15TF: Larrabee 2 - Knights Corner
36:08TF: Knights Landing
36:08TF: Knights Landing
36:08TF: Knights Landing
36:55TF: Knights Landing features: Conflict
36:55TF: Knights Landing features: Conflict
36:55TF: Knights Landing features: Conflict
38:39TF: AVX512
38:39TF: AVX512
38:39TF: AVX512
39:21TF: "Big Cores": Skylake Xeon, Canon Lake
39:21TF: "Big Cores": Skylake Xeon, Canon Lake
39:21TF: "Big Cores": Skylake Xeon, Canon Lake
40:22TF: Lessons: Lean on the compiler
40:22TF: Lessons: Lean on the compiler
40:22TF: Lessons: Lean on the compiler
40:41TF: Lessons: Every level of hardware shapes an ISA
40:41TF: Lessons: Every level of hardware shapes an ISA
40:41TF: Lessons: Every level of hardware shapes an ISA
42:03TF: No questions because we're out of time
42:03TF: No questions because we're out of time
42:03TF: No questions because we're out of time
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